View NOIS1SM0250A-HHC_9056259.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2014 january, 2017 ? rev. 11 1 publication order number: nois1sm0250a/d nois1sm0250a star250 250k pixel radiation tolerant cmos image sensor features ? 512 x 512 active pixels ? 25 m pixel size ? 1 inch optical format ? up to 30 frames per second (fps) at full resolution ? 8 mhz maximum data rate/master clock ? 3340 v.m 2 /w.s sensitivity ? 74 db (5000:1) dynamic range ? 76 e - ktc noise ? 4750 e - /s at rt dark current ? 5 v supply voltage ? operating temperature range ? ?40 c to +85 c ? gamma total dose radiation tolerance: ? increase in average dark current < 1 na/cm 2 after 3 mrad ? image operation with dark signal < 1 v/s after 10 mrad demonstrated (co60) ? proton radiation tolerance: ? 1% of pixels has an increase in dark current > 1 na/cm 2 after 3*10e10 protons at 11.7 mev ? sel threshold > 80 mev cm 3 mg -1 ? less than 350 mw power consumption ? these devices are pb ? free and are rohs compliant applications ? applications requiring higher pixel pitch ? scientific applications requiring radiation tolerance ? nuclear inspection overview the star250 sensor is a cmos active pixel sensor featuring 512 x 512 pixels on a 25 mm pitch, on chip fixed pattern noise (fpn) correction, a programmable gain amplifier, and a 10-bit adc. flexible operating (multiple windowing, sub-sampling) is possible by direct addressable x and y registers. the sensor has an outstanding radiation tolerance that is observed using proprietary technology modifications and design techniques. the star250 utilizes a bk7g18 glass lid with anti reflective coating. the cavity is filled with n 2 increasing the temperature operating range. ordering information marketing part number description package NOIS1SM0250A-HHC mono with bk7g18 glass 84 ? pin jlcc case 114ak nois1sm0250a-wwc mono wafer wafer sales note: refer to ordering code definition on page 2 for more information. www.onsemi.com figure 1. star250 photograph jldcc84 case 114ak
nois1sm0250a www.onsemi.com 2 ordering code definition o = opto n = on semiconductor star m = mono h= jlcc temperature range n o s1 a 0250 m sh h ? c s = standard process 0.25 mp resolution a= engineering model h= bk7g18 glass i i = image sensors marking the marking shall consist of a lead identification and traceability information. lead identification an index to pin 1 shall be located on the top of the package as shown in section package dimensions on page 21. the pin numbering is counter clock-wise, when looking at the top-side of the component. traceability information tests each component shall be marked such that complete traceability can be maintained. the component shall bear a number that is constituted as follows: orderable part number package mark: line 1 package mark: line 2 package mark: line 3 NOIS1SM0250A-HHC nois1sm0250a -hhc_nnnn awlyyww where nnnn- serialized number controlled manually by on semiconductor, belgium where awlyyww represents the lot assembly date marking diagram xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week nnnn = serial number 53 33 12 32 74 52 75 11 84 1
nois1sm0250a www.onsemi.com 3 specifications table 1. general specifications parameter specification remarks pixel architecture 3 transistor active pixel 4 diodes per pixel radiation-tolerant pixel design 4 photodiodes for improved mtf pixel size 25 x 25 m 2 resolution 512 x 512 pixels pixel rate 8 mps shutter type electronic integration time is variable, steps equal to the row readout time frame rate 29 full frames/second extended dynamic range double slope programmable gain programmable between x1, x2, x4, x8 selectable through pins g0 and g1 supply voltage v dd 5 v operational temperature range ?40 c to +85 c nitrogen in cavity package 84-pin jlcc table 2. electro-optical specifications parameter specification (typical) comment detector technology cmos active pixel sensor pixel structure 3-transistor active pixel 4 diodes per pixel radiation-tolerant pixel design 4 photodiodes for improved mtf photodiode high fill factor photodiode sensitive area format 512 by 512 pixels pixel size 25 m 2 x 25 m 2 spectral range 200 nm to 1000 nm see figure 2 and figure 3 quantum efficiency x fill fac- tor maximum 35% above 20% between 450 nm and 750 nm (metal fillfactor (mff) is 63%) full well capacity 311k electrons when output amplifier gain = 1 linear range within +1% 128k electrons when output amplifier gain = 1 output signal swing 1.68 v when output amplifier gain = 1 conversion gain 5.7 v/e - when output amplifier gain = 1 near dark temporal noise 76 e - dominated by ktc dynamic range 74 db (5000:1) at the analog output fpn 1 < 0.1% of full well (typical) measured local, on central image area 50% of pixels in the dark prnu (photo response nonuniformity) local: 1 = 0.39% of response global: 1 = 1.3% of response measured in central image area 50% of pixels, at qsat/2 average dark current signal 4750 e - /s at rt dsnu (dark signal nonuni- formity) 3805 e - /s rms at rt, scale linearly with integration time mtf horizontal: 0.36 vertical: 0.39 at 600 nm. optical cross talk 5% to nearest neighbor if central pixel is homogeneously illuminated
nois1sm0250a www.onsemi.com 4 table 2. electro-optical specifications parameter comment specification (typical) antiblooming capacity x 1000 to x 100 000 output amplifier gain 1, 2, 4, or 8 controlled by two bits windowing x and y 9-bit programmable shift registers indicate upper left pixel of each window electronic shutter range 1: 512 integration time is variable in time steps equal to the row readout time adc 10-bit adc linearity 3.5 counts inl missing codes none adc setup time 310 ns to reach 99% of final value adc delay time 125 ns power dissipation < 350 mw average at 8 mhz pixel rate spectral response curve figure 2. spectral response curve
nois1sm0250a www.onsemi.com 5 figure 3. uv region spectral response curve pixel profile figure 4. pixel profile the pixel profile is measured using the ?knife edge? method: the image of a target containing a black to white transition is scanned over a certain pixel with subpixel resolution steps. the sensor settings and illumination conditions are adjusted such that the transition covers 50% of the output range. the scan is performed both horizontal and vertical.
nois1sm0250a www.onsemi.com 6 electrical specifications absolute maximum ratings absolute ratings are those values beyond which damage to the device may occur. table 3. absolute maximum ratings star250bk7 characteristics limits units remarks min max any supply voltage ?0.5 +7 v voltage on any input terminal ?0.5 v dd + 0.5 v storage temperature ?40 +85 c ?40 +120 c maximum 1 hour sensor soldering temperature na 125 c hand soldering only. the sensor?s temperature during soldering should not exceed this limit. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 4. radiation tolerance parameter criterion qualification level gamma total dose radiation tolerance increase in average dark current < 1 na/cm 2 after 3 mrad see figure 5 image operation with dark signal < 1v/s 10 mrad demonstrated (co60) single (test) pixel operation with dark signal < 1v/s 24 mrad demonstrated (co60) proton radiation tolerance 1% of pixels has an increase in dark current > 1 na/cm 2 after 3 x 10^10 protons at 11.7 mev see figure 5 sel threshold > 80 mev cm 3 mg -1 to be confirmed
nois1sm0250a www.onsemi.com 7 figure 5 shows the increase in dark current under total dose irradiation. this curve is measured when the radiation is at high dose rate. annealing results in a significant dark current decrease. figure 5. dark current increase 0 0,2 0,4 0,6 0,8 1 1,2 1,4 0 total ionizing dos e [m r ad(si)] dark current increase [na/cm 2 ] 2 4 6 8 10 12 figure 6 shows the percentage of pixels with a dark current increase under 11.7 mev radiation with protons. figure 6. percentage of pixels with dark current increase
nois1sm0250a www.onsemi.com 8 dc operating conditions table 5. dc specifications symbol parameter (notes 1, 2 and 3) min typ max units v dd_ana analog supply voltage to imager part ? 5 ? v v dd_dig digital supply voltage to imager part ? 5 ? v v dd_adc_ana analog supply voltage to adc ? 5 ? v v dd_adc_dig digital supply voltage to adc ? 5 ? v v dd_adc_dig_3.3/5 supply voltage of adc output stage ? 3.3 to 5 ? v v ih logical ?1? input voltage 2.3 ? v dd v v il logical ?0? input voltage 0 ? 1 v v oh logical ?1? output voltage 4.25 4.5 ? v v ol logical ?0? output voltage ? 0.1 1 v v dd_pix pixel array power supply (default 5 v, the device is then in ?soft reset?. to avoid the image lag associated with soft reset, reduce this voltage to 3?3.5 v ?hard reset?) ? 5 ? v v dd_resl reset power supply ? 5 ? v 1. all parameters are characterized for dc conditions after establishing thermal equilibrium. 2. unused inputs must always be tied to an appropriate logic level, for example, either vdd or gnd. 3. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. take norm al precautions to avoid applying any voltages higher than the maximum rated voltages to this high impedance circuit.
nois1sm0250a www.onsemi.com 9 sensor architecture y-start registeer-decoder 9 10 d9...d0 clk_adc ain column amplifiers 512 512 ld_x rst sig progr. gain amplifier blackref cal g0 g1 sync_yl clk_yl ld_y 9 9 512 y address decoder / shift register 512 rst sel col y address decoder / shift register 10-bit adc clk_yr syncyr a8...a0 aout 9 clkx sync_x x-start register figure 7. star250 schematic x address decoder / shift register r s pixel array 512 by 512 pixels the base line of the star250 sensor design consists of an imager with a 512 by 512 array of active pixels at 25 m pitch. the detector contains on-chip correction for fpn in the column amplifiers, a programmable gain output amplifier, and a 10-bit adc. through additional preset registers, the start position of a window can be programmed to enable fast read out of only part of the detector array. pixel structure the image sensor consists of several building blocks as outlined in figure 7. the central element is a 512 by 512 pixel array with square pixels at 25 m pitch. unlike classical designs, the pixels of this sensor contain four photodiodes. this configuration enhances the mtf and reduces the prnu. figure 8 shows an electrical diagram of the pixel structure. the four photodiodes are connected in parallel to the reset transistor (t1). transistor t2 converts the charge, collected on the photo diode node, to a voltage signal that is connected to the column bus by t3. the reset and read entrance of the pixel are connected to one of the y shift registers. figure 8. star250 pixel structure t1 t2 t3 read column bus reset
nois1sm0250a www.onsemi.com 10 shift registers the shift registers are located next to the pixel array and contain equal number of outputs and pixel array rows. they are designed as ?1-hot? registers, (yl and yr shift register) each allowing selection of one row of pixels at a time. a clock pulse moves the pointer one position down the register resulting in the selection of every individual row for either reset or readout. the spatial offset between the two selected rows determines the integration time. a synchronization pulse to the shift registers loads the value from a preset register into the shift register forcing the pointer to a predetermined position. windowing in the vertical (y) direction is achieved by presetting the registers to a row that is not the first row and by clocking out only the required number of rows. column amplifiers all outputs from the pixels in a column are connected in parallel to a column amplifier. this amplifier samples the output voltage and the reset level of the pixel whose row is selected at that moment and presents these voltage levels to the output amplifier. as a result, the pixels are always reset immediately after readout as part of the sample procedure and the maximum integration time of a pixel is the time between two read cycles. electronic shutter in a linescan integrating imager with electronic shutter, there are two continuous processes of image gathering. the first process resets lines in a progressive scan. at line reset, all the pixels in a line are drained from any photo charges collected since their last reset or readout. after reset, a new exposure cycle starts for that particular line. the second process is the actual readout, which also happens in an equally fast linewise progressive scan. during readout, the photo charges collected since the previous reset are converted into an output voltage. this is then passed on pixel by pixel to the imager?s pixel serial output and adc. readout is destructive, meaning the accumulation of charges from successive exposure phases is not possible in the present architecture. the star250 has two y shift registers; yl and yr. one is used to read out a line (yl) and the other is used to reset a line (yr). the integration time is equal to the time between the last reset and readout of that line, see figure 9. the integration time is calculated as follows: integration time = (nr. lines * (rbt + pixel period * nr. pixels)) with: ? nr. lines: number of lines between readout and reset (y). ? nr. pixels: number of pixels read out each line (x). ? rbt: row blanking time = 3.2 s (typical). ? pixel period: 1/8 mhz = 125 ns (typical). reset line read line x y x y time axis line num ber frame tim e integration time reset sequence figure 9. electronic shutter
nois1sm0250a www.onsemi.com 11 programmable gain amplifier the signal from the column amplifiers is fed to an output amplifier with four presettable gains (adjustable with pins g0 and g1). the offset correction of this amplifier is done through a black reference procedure. the signal from the output amplifier is externally available on the analog output terminator of the device. analog-to-digital converter the on-chip 10-bit adc is electrically separated from the other circuits of the device. the adc conversion range is set by the voltages on vlow_adc (pin 47) and vhigh_adc (pin 70). make voltages on these pins equal to about 2 v on vlow_adc and 4 v on vhigh_adc. the voltages are set by connecting vlow with 1.2 k to gnd and vhigh_adc with 560 to v dd . this way, a resistor ladder is created as shown in figure 10. figure 10. adc resistor ladder r adc_vhigh external internal r adc r adc_vlow external pin 70: vhigh_adc pin 47: vlow_adc the internal adc resistance varies according to temperature. the resistance value increases approximately 4.4 / c with increasing temperature. if the adc range is set externally with resistors, the conversion range may vary with temperature. this effect is cancelled out by not making use of resistors but directly applying voltages on vlow_adc and vhigh_adc. timing and readout of image sensor image readout procedure a preamble or initialization phase is irrelevant. the sensor is read out continuously. the first frame is generally saturated and useless because there is no preceding reset of each pixel. image readout in an infinite uninterrupted loop, follow these steps for every line: 1. synchronize the read (yl) and/or reset (yr) registers: ? sync_yl - to reinitiate the readout sequence to row position y1 ? sync_yr - to reinitiate the reset pointer to row position y1 for all other lines do not pulse one of these sync_y signals. 2. operate the double sampling column amplifiers with two resets. apply one to reset the line that is currently selected to produce the reset reference level for the double sampling column amplifiers. apply the other reset to another line depending on the required integration time reduction. 3. perform a line readout: ? reset the x read address shift register to the value in its shadow register (x1). ? perform a pixel readout operation, operating the track/hold and the adc. ? shift the x read address shift register one position further. ? shift the y read and reset address shift registers one position further. if either of y read or reset address shift register comes to the end of the pixel array (or the roi), wrap it around to the start position by pulsing sync_yl. readout timing the actual line readout process starts with addressing the line to read. this is done either by initializing the yl pointer with a new value or by shifting it one position beyond its previous value. (addressing the line has reset, yr is done in an analogous fashion). during the ?blanking time?, after the new line is addressed on the sensor, the built-in column-parallel double sampling amplifiers are operated. this renders offset-corrected values of the line under readout. after the blanking time, the pixels of the row addressed by yl are read by multiplexing all the pixels one by one to the serial output chain. the pixel is selected by the x pointer and that pointer is either initialized with a new value or an increment of the previous position. the time between row resets and their corresponding row readouts is the ef fective exposure time (or integration time). this time is proportional to the number of lines (delaylines) between the line currently under reset and the line currently under readout: delaylines = (yr - yl+1).
nois1sm0250a www.onsemi.com 12 this time is also equal to the delay between the sync_yr pulse and the subsequent sync_yr. the effective integration time tint is calculated as delaylines x line time. the line time is a function of four terms: the time to output the desired number of pixels in the line (wframe) and the overhead (?blanking?) time needed to select a new line and perform the double sampling and reset operations. t13 t10 t2 t9 t16 t15 t17 t14 t12 t1 t3 t7 t4 t6 t4 t11 t5 t8 time available for read out of row y row blanking time row y-1 cal row start address ld_y may occur at any moment, persumably once per sequence of frames once per frame s reset r l/r figure 11. basic readout timing sync_yr is not identical to sync_yl. sync_yr is used in electronic shutter operation. the clk_yr is driven identical to clk_yl, but the sync_yr pulse leads the sync_yl pulse by a certain number of rows. this lead time is the effective integration (electronic shutter ~) time. relative to the row timing, both sync pulses are given at the same time position, once for each frame, but during different rows. sync_yl is pulsed when the first row is read out and sync_yr is pulsed for the electronic shutter to start for this first row. cal is pulsed on the first row too, 2 s later than sync_yl. the minimal idle time is 1.4 s (before starting reading pixels). however, do not read out pixels during the complete row initialization process (in between the rising edge on s and the falling edge on l/r). in this case, the total idle time is minimal. this timing assumes that the y start register was loaded in advance, which can occur at any time but before the pulse on sync_yl or sync_yr.
nois1sm0250a www.onsemi.com 13 table 6. readout timing specifications symbol min typ description t1 1.8 s ? delay between selection of new row by falling edge on clk_yl and falling edge on s. minimal value. normally, clk_yr is low already at the end of the previous sequence. t2 1.8 s ? delay between selection of new a row by sync_yl and falling edge on s. t3 0.4 s ? duration of s and r pulse. t4 0.1 s ? duration of reset pulse. t5 t4 + 40 ns 0.3 s l/r pulse must overlap second reset pulse at both sides. t6 0.8 s ? delay between falling edge on reset and falling edge on r. t7 20 ns 0.1 s delay between falling edge on s and rising edge on reset. t8 0 1 s delay between falling edge on l/r and falling edge on clk_y. t9 100 ns 1 s duration of cal pulse. the cal pulse is given once each frame. t10 0 2 s delay between falling edge of sync_yl and rising edge of cal pulse. t11 40 ns 0.1 s delay between falling edge on r and rising edge on l/r. t12 0.1 s 1 s delay between rising edge of clk_y and falling edge on s. t13 ? 0.5 s pulse width sync_yl/yr. t14 ? 0.5 s pulse width clk_yl/yr. t15 10 ns ? address setup time. t16 20 ns ? load x/y start register value. t17 10 ns ? address stable after load. t18 10 ns ? t19 20 ns ? sync_x pulse width. sync_x while clk_x is high. t20 10 ns ? t21 ? 40 ns analog output is stable during clk_x low. t22 ? 40 ns clk_x pulse width: during this clock phase the analog output ramps to the next pixel level. t23 ? 125 ns adc digital output stable after falling edge of clk_adc. loading the x and y start positions the start positions (start addresses) for region of interest (roi) are preloaded in the x or y start register . they become effective by the application of the sync_x, sync_yl and/or sync_yr. the start x or y address must be applied to their common address bus and the corresponding ld_x or ld_y pin must be pulsed. on each falling edge of clk_x, a new pixel of the same row (line) is accessed. the output stage is in hold when clk_x is low and starts generating a new output after a rising edge on clk_x. the following timing constraints apply: load the x or y start addresses in advance, before the x or y shift registers are preset by a sync pulse. however, if necessary, they can be loaded just before the sync_x or sync_y pulse as shown in figure 12. for example, the x start register can be loaded during the row idle time. the y start register can be loaded during readout of the last row of the previous frame. if the x or y start address does not change for later frames, it does not need to be reloaded in the register.
nois1sm0250a www.onsemi.com 14 figure 12. timing to load x and y registers row blanking time time available for read out of row y column start address may occur at any moment in time ld_x t15?t17 t16 t19 t18t20 t21 t22 pixel 1 pixel 2 pixel 3 t23 pixel 1 pixel 2 adc out clk adc analog output clk_x sync_x other signals tie select signal to v dd for normal operation. this signal is added for diagnostic reasons and inhibits the pixel array operation when held low. the cal signal sets the output amplifier dc offset level. when this signal is active (high) the pixel array is internally disconnected from the output amplifier, its gain is set to unity and its input signal is connected to the black_ref input. perform this action at least once for each frame. eos_x, eos_yl, and eos_yr produce a pulse when the respective shift register comes at its end. these outputs are used mainly during testing to verify proper operation of the shift registers. testdiode and testpixel_array are connections to optical test structures that are used for electro optical evaluation. testdiode is a plain photodiode with an area of 14 x 5 pixels. testpixel_array is an array (14 x 5) of pixels where the photodiodes are connected in parallel. these structures measure the photocurrent of the diodes directly. testpixel_reset and testpixel-out are connections to a single pixel that are used for testing.
nois1sm0250a www.onsemi.com 15 pin list table 7. power supply connections pin pin name pin description 10 v dd_ana analog power supply 5 v 11 v dd_dig digital power supply 5 v 31 v dd_amp power supply of output amplifier 5 v 33 v dd_dig digital power supply 5 v 34 v dd_ana analog power supply 5 v 49 v dd_resr reset power supply 5 v 50 v dd_dig digital power supply 5 v 53 v dd_adc_ana adc analog power supply 5 v 66 v dd_adc_ana adc analog power supply 5 v 67 v dd_adc_dig adc digital power supply 5 v 69 v dd_adc_dig_3.3/5 adc 3.3 v power supply for digital output of adc for interface with 5 v external system: connect to v dd_adc_dig for interface with 3.3 v external system: connect to 3.3 v power supply 52 76 v dd_pix pixel array power supply [default: 5 v, the device is then in ?soft reset?. to avoid the image lag associated with soft reset, reduce this voltage to 3 ? 3.5 v ?hard reset?] 78 v dd_dig digital power supply 5 v 79 v dd_resl reset power supply 5 v table 8. ground connections pin pin name pin description 9 gnd_ana analog ground 12 gnd_dig digital ground 30 gnd_amp ground of output amplifier 32 gnd_dig digital ground 35 gnd_ana analog ground 51 gnd_dig digital ground 54 gnd_adc_ana adc analog ground 65 gnd_adc_ana adc analog ground 68 gnd_adc_dig adc digital ground 77 gnd_dig digital ground table 9. digital input signals pin pin name pin description 1 s control signal for column amplifier apply pulse pattern; see figure 11. 2 r control signal for column amplifier apply pulse pattern; see figure 11. 3 reset resets row indicated by left/right shift register high active (1= reset row) apply pulse pattern; see figure 11. 4 select selects row indicated by left/right shift register high active (1=select row) apply 5 v dc for normal operation
nois1sm0250a www.onsemi.com 16 table 9. digital input signals pin pin description pin name 5 l/r use left or right shift register for select and reset 1 = left / 0 = right; see figure 11. 6 a0 start address for x and y pointers (lsb) 7 a1 start address for x and y pointers 8 a2 start address for x and y pointers 13 a3 start address for x and y pointers 14 a4 start address for x and y pointers 15 a5 start address for x and y pointers 16 a6 start address for x and y pointers 17 a7 start address for x and y pointers 18 a8 start address for x and y pointers (msb) 19 ld_y latch address (a0 ? a8) to y start register (0 = track, 1 = hold) 20 ld_x latch address (a0 ? a8) to x start register (0 = track, 1 = hold) 21 clk_yl clock yl shift register (shifts on falling edge) 22 sync_yl sets yl shift register to location preloaded in y start register low active (0=sync) apply sync_yl when clk_yl is high 24 clk_x clock x shift register (output valid and s when clk_x is low) 25 sync_x sets x shift register to location preloaded in x start register low active (0=sync) apply sync_x when clk_x is high after sync_x, apply falling edge on clk_x, and rising edge on clk_x 27 clk_yr clock yr shift register (shifts on falling edge) 28 sync_yr sets yr shift register to location preloaded in y start register low active (0=sync) apply sync_yr when clk_yr is high 36 cal initialize output amplifier output amplifier will output blackref in unity gain mode when cal is high (1) apply pulse pattern (one pulse per frame); see figure 11. 37 g0 select output amplifier gain value: g0 = lsb; g1 = msb 00 = unity gain; 01 = x2; 10 = x4; 11 = x8 38 g1 idem 71 clk_adc adc clock adc converts on falling edge 75 bitinvert 1 = invert output bits 0 = no inversion of output bits 80 tri_adc tristate control of digital adc outputs 1 = tristate; 0 = output
nois1sm0250a www.onsemi.com 17 table 10. digital output signals pin pin name pin description 23 eos_yl end-of-scan of yl shift register low first clock period after last row (low active) 26 eos_x end-of-scan of x shift register low first clock period after last active column (low active) 29 eos_yr end-of-scan of yr shift register low first clock period after last row (low active) 55 d0 adc output bit (lsb) 56 d1 adc output bit 57 d2 adc output bit 58 d3 adc output bit 59 d4 adc output bit 60 d5 adc output bit 61 d6 adc output bit 62 d7 adc output bit 63 d8 adc output bit 64 d9 adc output bit (msb) table 11. analog input signals pin pin name pin description 39 nbiasarr connect with 470 k to v dd and decouple to ground with a 100 nf capacitor. 40 pbias connect with 39 k to ground and decouple to v dd with a 100 nf capacitor for 8 mhz pixel rate. (lower resistor values yield higher maximal pixel rates at the cost of extra power dis- sipation). 41 nbias_amp output amplifier speed/power control. connect with 51 k to v dd and decouple with 100 nf to gnd for 8 mhz output rate (lower resistor values yield higher maximal pixel rates at the cost of extra power dissipation). 42 blackref control voltage for output signal offset level. buffered on-chip, the reference level can be generated by a 100 k resistive divider. connect to 2 v dc for use with on-chip adc. 44 in_adc input, connect to sensor output. input range is between 2 and 4 v (vlow_adc and vhigh_adc). 45 nbiasana2 connect with 100 k to v dd and decouple to gnd. 46 nbiasana connect with 100 k to v dd and decouple to gnd. 47 70 vlow_adc vhigh_adc low reference and high reference voltages of adc should be about 2 v and 4 v. the required voltage settings on vlow_adc and vhigh_adc can be approximated by tying vlow_adc with 1.2 k to gnd and vhigh_adc with 560 to v dd . 48 g_ab antiblooming drain control voltage: default: connect to ground. the antiblooming is operational but not maximal. apply 1 v dc for improved antiblooming. 72 pbiasdig2 connect with 100 k to gnd and decouple to v dd . 73 pbiasencload connect with 100 k to gnd and decouple to v dd . 74 pbiasdig1 connect with 47 k to gnd and decouple to v dd . table 12. analog output signals pin pin name pin description 43 out analog output signal are connected to the analog input of the adc.
nois1sm0250a www.onsemi.com 18 table 13. test structures pin pin name pin description 81 testdiode plain photo diode, size: 14 x 25 pixels. must be left open for normal operation. 82 testpix array array of test pixels, connected in parallel (14 x 25 pixels). must be left open for normal operation. 83 testpixel_reset reset input of single test pixel. must be tied to gnd for normal operation. 84 testpixel_out output of single test pixel. must be left open for normal operation. glass lid specifications figure 13. geometrical characteristics (in mm)
nois1sm0250a www.onsemi.com 19 package dimensions jldcc84 case 114ak issue a table 14. package specifications type jlcc-84 material black alumina ba-914 thermal expansion coefficient 7.6 x 10 -6 /k
nois1sm0250a www.onsemi.com 20 table 15. mechanical specifications characteristics limits units min typ max package tolerance ? ? 0.15 mm die position, x offset ?0.05 0 0.05 mm die position, y offset ?0.018 ? 0.118 mm die position, planarity ?0.05 0 0.05 mm die position, y tilt ?0.05 0 0.05 mm note: min and max limits are not measured on every unit, but guaranteed by assembly process. die alignment the die is aligned manually in the package to a tolerance of 50 m and the alignment is verified after hardening the die adhesive. all dimensions in figure 14 are in mm. die adhesive: 0.08+0.02 window adhesive: 0.08+0.02 glass window: 1.0+/-0.05 bonding cavity: 0.508+0.051 section a a - drawing not to scale 68 center of cavity and of fpa center of silicium offset between center of silicium and center of cavity: x: 0 y: 68 m parallelism in x and y within + 50 m pin 1 a a figure 14. die alignment die cavity: 0.508+0.051 die: 0.508+0.01
nois1sm0250a www.onsemi.com 21 additional references and resources application notes and other resources can be found linked to the product web page at www.onsemi.com . additional information on this device may also be available in the image sensor portal , accessible within the myon section of www.onsemi.com . a signed nda is required to access the image sensor portal ? please see your on semiconductor sales representative for more information. for information on esd and cover glass care and cleanliness, please download the application note image sensor handling and best practices (an52561/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions document from www.onsemi.com . for information on return material authorization procedures, please refer to the rma policy procedure document from www.onsemi.com . the product acceptance criteria document, which lists criteria to which this device is tested prior to shipment, is available upon request.
nois1sm0250a www.onsemi.com 22 acronyms acronym definition adc analog to digital convertor cis cmos image sensor cmos complementary metal oxide semiconductor cy cypress dc dark current dnl differential nonlinearity ds double sampling dsnu dark signal nonuniformity esd electrostatic discharge ff fill factor fpn fixed pattern noise fps frames per second fs frame start fs full scale i/o input/output img image inl integral nonlinearity ip intellectual property ldo low drop-out lsb least significant bit lvds low voltage differential signaling mbs mixed boundary scan acronym definition mbps megabit per second mcis multifield point cmos image sensor mff metal fill factor mim metal-insulator-metal mp megapixel mrad megaradiation msb most significant bit msps megasamples per second mtf modulation transfer function mux multiplexer pcb printed circuit board pll phase-locked loop pls parasitic light sensitivity prbs pseudo random bit stream prnu photo response nonuniformity psn photon shot noise psnl pixel storage node leakage qc quantum conversion qe quantum efficiency qfw pixel full-well charge rms root mean square roi region of interest
nois1sm0250a www.onsemi.com 23 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. con- version gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. dnl differential nonlinearity (for adcs) dsnu dark signal nonuniformity. this parameter characterizes the degree of nonuniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixe l array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response nonuniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and con- verting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is operated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel de- signs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodiode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wave- length. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
nois1sm0250a www.onsemi.com 24 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nois1sm0250a/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

▲Up To Search▲

Price & Availability of NOIS1SM0250A-HHC

	To Download NOIS1SM0250A-HHC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .